1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of semiconductor devices, and, more specifically, to various methods of removing portions of at least one fin structure so as to from isolation regions when forming FinFET semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a traditional FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap layer 20. The fins 14 are formed by etching a plurality of trenches 13 into the substrate 12. A recessed layer of insulating material (not shown) is normally positioned in the trenches 13 between the fins 14. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode (not separately shown) for the device 10. The fins 14 have a three-dimensional configuration: a height 14H, a width 14W and an axial length 14L. The axial length 14L corresponds to the direction of current travel, i.e., the gate length (GL) of the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 is the channel region of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes to form additional semiconductor material on the portions of the fins 14 in the source/drain region.
Both planar transistor devices and FinFET transistor devices have an isolation structure, e.g., a shallow trench isolation structure, that is formed in the semiconducting substrate around the device so as to electrically isolate the transistor device. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures into the substrate and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the transistor devices. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching additional trenches into the substrate to thereby define the fins. As FinFET devices have been scaled (i.e., reduced in physical size) to meet ever increasing performance and size requirements, the width 14W of the fins 14 has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm. As the dimensions of the fins 14 became smaller, problems arose with manufacturing the isolation structures before the fins 14 were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate.
Various techniques have been employed to try to overcome the above-mentioned problems. One manufacturing technique involves initially forming trenches 13 in the substrate 12 to define multiple “fins” that extend across the substrate 12, and thereafter removing some of the fins 14 (or portions thereof) where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 14 to very small dimensions due to the more uniform etching environment in which the etching process that forms the trenches 13 is performed.
As indicated above, after the trenches 13 are formed, some portion of the fins 14 must be removed to create room for or define the spaces where isolation regions will ultimately be formed. There are two commonly employed techniques for accomplishing the goal of removing the desired number and portions of the fins 14. One such removal process is typically referred to as “Fins-cut-First,” as will be described with reference to FIGS. 1B-1E. FIG. 1B depicts the device 10 after a patterned hard mask layer 30, e.g., comprised of a patterned layer of silicon nitride (pad-nitride) and a patterned layer of silicon dioxide (pad-oxide), was formed above the substrate 12 in accordance with the desired fin pattern and pitch. In the depicted example, only a single fin will be removed, i.e., the fin 14 corresponding to the feature 30A, to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed. Of course, the entire axial length 14L of the fin 14 need not be removed, but it may be in some applications.
FIG. 1C depicts the device 10 after a patterned masking layer 34, e.g., a patterned layer of photoresist, was formed above the patterned hard mask layer 30. The patterned masking layer 34 has an opening that exposes the feature 30A for removal.
FIG. 1D depicts the device 10 after an etching process was performed through the patterned masking layer 34 so as to remove the exposed feature 30A of the patterned hard mask layer 30.
FIG. 1E depicts the device 10 after the patterned masking layer 34 was removed and after an etching process was performed through the patterned hard mask layer 30 (without the feature 30A) so as to define full-depth trenches 13 in the substrate 12 that define the fins 14. Due to the removal of the feature 30A, this etching process removes the portions of the substrate 12 that would have otherwise formed a fin 14 in the area under the feature 30A. One problem with the “fins-cut-first” approach is that it inevitably causes different fin sizes, i.e., the dimensions 14X and 14Y are different. This is especially true between fins 14 inside an array of fins and the fins at the edge of the active region that is close to the isolation region. These dimensional variations occur due to etch loading effects wherein there are different etch rates and etch profiles due to differing patterning densities, pitch, etc.
FIG. 1F depicts the device 10 after several process operations were performed. First, a layer of insulating material 36, such as silicon dioxide, was formed so as to overfill the trenches 13. A chemical mechanical polishing (CMP) process was then performed to planarize the upper surface of the insulating material 36 with the top of the patterned hard mask 30. Thereafter, an etch-back process was performed to recess the layer of insulating material 36 between the fins 14 and thereby expose the upper portions of the fins 14, which corresponds to the final fin height of the fins 14. At this point in the process, the patterned hard mask 30 may or may not be thereafter removed. Next, the gate structure (not shown) of the device 10 may be formed using either gate-first or gate-last manufacturing techniques.
Another fin removal process is typically referred to as “Fins-cut-Last,” as will be described with reference to FIGS. 1G-1J. FIG. 1G depicts the device 10 after the patterned hard mask layer 30 was formed above the substrate 12 in accordance with the desired fin pattern and pitch. As before, in the depicted example, only a single fin will be removed, i.e., the fin 14 corresponding to the feature 30A, to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed.
FIG. 1H depicts the device 10 after an etching process was performed through the patterned hard mask layer 30 so as to define full-depth trenches 13 in the substrate 12 that define the fins 14. Note that, in the Fins-cut-Last approach, the size of the fins tends to be more uniform, i.e., the dimension 14A is approximately equal to the dimension 14B. This is primarily due to the fact that, in this approach, fins 14 are initially formed everywhere on the wafer with a uniform width and fin pitch, and there is no undesirable etch loading effects.
FIG. 1I depicts the device 10 after several process operations were performed. First, a layer of insulating material 38, such as silicon dioxide, was formed so as to overfill the trenches 13. Then a CMP process was performed to planarize the upper surface of the layer of insulating material 38 with the patterned hard mask layer 30. Next, a patterned masking layer 40, e.g., a patterned layer of photoresist, was formed above the layer of insulating material 38. The patterned hard mask layer 40 has an opening that is positioned above the underlying fin 14 (or portion thereof) that is to be removed.
FIG. 1J depicts the device 10 after one or more etching processes were performed to remove the exposed portions of the layer of insulating material 38, the exposed portions of the hard mask layer 30, i.e., the feature 30A, and the underlying fin 14 by forming a trench 42 in the substrate 12. Inevitably, there will be some tapering of the sidewalls of the trench 42. Although not depicted in the drawings, after the trench 42 is formed, the patterned masking layer 40 will be removed and additional oxide material (not shown) will be formed through the opening 42A in the trench 42 where the fin 14 was removed. Then a chemical mechanical polishing (CMP) process will be performed to planarize the upper surface of all of the insulating materials with the top of the patterned hard mask 30. Thereafter, the isolation regions between devices will be masked and an etch-back process will be performed to recess the layer of insulating material 38 between the fins 14 for each device and thereby expose the upper portions of the fins 14, which corresponds to the final fin height of the fins 14.
FIGS. 1K-1L are simplistic plan views depicting the basic Fins-Cut-Last process flow. As shown therein, a plurality of fins 14 were formed above the substrate, and a patterned etch mask 50, a so-called “cut-mask” was formed above the fins. FIG. 1L depicts the product after the exposed portions of the fins 14 were removed, after the etch mask 50 was removed, and after a recessed layer of insulating material 52 was formed between the cut fins 14.
One problem with the fins-cut-last approach is that if the size (CD) of the opening 42A of the trench 42 is relatively large, then there is less margin for misalignment error when removing the unwanted fin, i.e., there is less margin for error so as to avoid damage to fins adjacent the fin that is removed when the trench 42 is etched. Additionally, although not depicted, if the size of the opening 42A is kept small, there will typically be some residual portion of the fin 14 remaining at the bottom of the trench 42. Conversely, if the size of the opening 42A is increased in an effort to insure complete removal of the unwanted fin at the bottom of the trench 42, then there is a much greater likelihood of damaging the fins adjacent the trench 42 when the trench 42 is etched into the substrate 12. These issues only get worse as the depth of the trench 42 increases and the lateral spacing between adjacent fins 14 gets smaller as is required for advanced devices. The chances for lateral misalignment of the opening 42A in the patterned etch mask 40 is also greater when forming more densely packed fins, which leads to increased chances of damaging fins that are adjacent to the sidewalls of the trench 42.
In many applications, it would be desirable to only remove a portion of a single fin so as to form a very narrow isolation region between two active devices. However, as fin pitches have decreased, it is very difficult to remove only a single fin. In some cases, manufacturers have instead removed portions of two adjacent fins rather than deal with the problems associated with trying to remove only a single fin. This results in a wider isolation region which, in turn, consumes additional valuable plot space on the substrate.
The present disclosure is directed to various methods that may solve or reduce one or more of the problems identified above.